The schematic diagram and related TE performance curves of the optimization strategy (IMAGE)

Science China Press

The schematic diagram and related TE performance curves of the optimization strategy

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(a) The schematic diagram shows the optimization route for the TE performance in this work. The interstitial Cu was introduced into the van der Waals layer of Bi2Te2.7Se0.3, effectively suppressing the intrinsic defects in the material. Further, a two-step hot deformation process was employed to prepare the highly textured Cu0.01Bi2Te2.7Se0.3. (b) The room temperature carrier mobility data indicating the interstitial Cu and texturation process is effective in improving the mobility of Cu0.01Bi2Te2.7Se0.3. (c) Temperature dependent ZT of pristine Bi2Te2.7Se0.3 and textured Cu0.01Bi2Te2.7Se0.3. (d) Cooling performance of a 127-pair TEC module based on textured Cu0.01Bi2Te2.7Se0.3 and commercial p-type (Bi,Sb)₂Te₃ at different temperatures. (D127 represents 127-pair device, and D31 represents 31-pair device). (e) A comparison of device energy conversion efficiency for 7-pair TEG module and other reported Bi2Te3-based TE modules.

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