Fully automated system for simultaneous grinding of silicon and copper

To improve the performance of semiconductor circuits, “3D packaging technology,” which integrates circuits in three dimensions, has been attracting attention. However, due to issues like high cost and low yield rates (non-defective product rates), its practical application is limited to only a few high-performance devices. In the development project "Fully Automated Grinding Equipment for Through-Si Via Wafers" of the Japan Science and Technology Agency's (JST) Adaptable and Seamless Technology Transfer Program through Target-driven R&D (A-STEP) NexTEP-A type, a fully automated grinding system that exposes through-Si via from the backside of silicon (Si) wafers was developed to reduce variation in the length of the through-Si via, which is a factor in yield loss, and for achieving stable simultaneous grinding of Si and copper (Cu) in the metal part. Residual Cu removal from wafers was also successfully achieved.

JST certified the development results of the fully automated grinding system for through-Si via wafers as a success. This development project based on the research results of Dr. Naoya Watanabe, Senior Researcher, Semiconductor Frontier Research Center, National Institute of Advanced Industrial Science and Technology, and is being developed for practical use at Okamoto Machine Tool Works, Ltd.

This equipment uses grinding wheels with many pores that are less likely to clog, and an automatic wafer thickness correction function to minimize variation in the length of through-Si via^*1), enabling stable and precise simultaneous grinding of silicon and copper. In addition, by cleaning wafers after grinding^*2) with alkaline ionized water, followed by electroless plating and silicon wet etching^*3), the residual Cu on the Si was successfully removed below the typical metal concentration, while preventing Cu from dissolving out of the through-Si via area.

This system will not only improve the efficiency of the through-Si via formation process, but also enable direct stacking at the wafer level (stacking without using bumps), which is expected to result in low costs and high yields in the through-Si via formation process. In the future, through collaboration with device manufacturers, it is expected that this technology can be applied to various devices, and that the performance of semiconductor circuits will be improved.

<Notes>

*1) Through-Si via:

An electrode formed through the semiconductor wafer (chip) from the front to back surface. The metal part of the electrode is formed mainly of Cu.

*2) Grinding:

A process in which a grinding wheel is rotated and pressed against a workpiece (in this case, a semiconductor wafer) to grind the workpiece and finish it to the desired shape. A grinding wheel comprises hard grains called abrasive grains hardened with a bond material.

*3) Si wet and dry etching:

Si wet etching is the processing wafers by selectively dissolving them using chemicals (etchant). Si dry etching is the processing wafers using high-vacuum plasma.