The fabrication of ultrathin 8-nm Sn-doped Ga2O3 FETs for power nanodevices via co-sputtering. (IMAGE)
Caption
(a) Schematic diagram of Sn-doped Ga2O3 film preparation via co-sputtering at room temperature. (b) Photograph of deposited Sn-doped Ga2O3 films on a 4-inch Si/SiO2 substrate. (c) Schematic diagram of the conductive atomic force microscopy (C-AFM) measurement setup for ultrathin Sn-doped Ga2O3 films on Si-based wafers. (d) Surface current distribution images (3 μm × 3 μm) via C-AFM for Sn-doped Ga2O3 and pristine Ga2O3 films measured at 3 V. (e) Surface current values of the films along the white dashed lines in (d). (f) Transfer curve of the 8-nm Sn-doped Ga2O3 FET with SiO2 gate dielectric under a drain voltage of 120 V. (g) Breakdown characteristics of the FET shown in panel (f).
Credit
©Science China Press
Usage Restrictions
Use with credit.
License
Original content