News Release

Researchers develop a high-efficiency buck-boost DC-DC converter

Reports and Proceedings

University of Science and Technology of China

A 98.6%-Peak-Efficiency 1.47A/mm2Current-Density Buck-Boost Converter with Always Reduced Conduction Loss

image: The architecture of the chip view more 

Credit: Image by Prof. Cheng’s team

A high-efficiency buck-boost DC-DC converter was developed by the research team headed by Prof. CHENG Lin from the School of Microelectronics at the University of Science and Technology of China (USTC) of the Chinese Academy of Sciences (CAS). The converter made its debut at the IEEE International Solid-State Circuits Conference (ISSCC), which is the top conference in integrated circuit design. This is the third time that Cheng’s team has published their work in ISSCC, entitled "A 98.6%-Peak-Efficiency 1.47A/mm2Current-Density Buck-Boost Converter with Always Reduced Conduction Loss".

Buck-boost converters are widely used in mobile electronic devices powered by lithium batteries to convert the battery voltage to a fixed voltage of about 3.4 V to power modules. The converter is expected to maintain high efficiency over the full battery voltage range to extend the battery life. In addition, the miniaturization of mobile electronic devices calls for a high current density of converters.

In this work, Cheng’s team proposed a novel Buck-Boost converter topology containing only four low-voltage power tubes, one flying capacitor, and one inductor. This structure was the only design so far to keep four power tubes and one flying capacitor without high voltage resistance. Besides, with the assistance of the flying capacitor, the inductor current and the conduction loss of this structure were effectively reduced in the full battery voltage range.

The test results revealed that the chip achieved a peak efficiency of 98.6% and a maximum output current of 2.5 A with a chip area of 1.7 mm2. Compared with other studies, this design achieved the highest efficiency at full voltage conversion ratio and the highest current density at the lowest chip cost, striking a perfect balance between efficiency and current density.

 


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