In our communication-centered society, Moore’s law sets up a high expectation on the increasing rate of the packing density of Si-based transistors. This drives the search for thickness-scalable high dielectric constant (high k) gate layers. Current material candidates, from simple binary oxides to complex polar oxides, all have failed to solve the “polarizability-scalability-insulation robustness” trilemma (Fig. 1 a-b), hence contributing to the sum total of issues threatening the continuation of the Moore’s law.
A team of material scientists led by Jun Ouyang from Qilu University of Technology in Jinan, China recently proposed a solution to this trilemma on gate layers, which is an ultrathin film of a ferroelectric oxide in its superparaelectric (SPE) state. In the SPE, its polar order becomes local and dispersed with a crystalline size down to a few nanometers (“nanometer polar clusters”), leading to an excellent dimensional scalability and an excellent field stability/linearity of the k value (Fig. 1c).
The team published their research article in Journal of Advanced Ceramics on April 30, 2024.
“In the SPE, its polar order becomes local and is dispersed in an amorphous matrix with a crystalline size down to a few nanometers, leading to an excellent dimensional scalability and a good field-stability of the k value. As an example, a stable high k value (37±3) is shown in ultrathin SPE films of (Ba0.95,Sr0.05)(Zr0.2,Ti0.8)O3 (BSZT) sputter-deposited on LaNiO3-buffered Pt/Ti/ SiO2/(100)Si down to a 4 nm thickness at room temperature, leading to a small equivalent oxide thickness (EOT) of ~0.46 nm. ” said Jun Ouyang, senior author of the research article, professor in the School of Chemistry and Chemical Engineering and team leader of Advanced Energy Materials and Chemistry at Qilu University of Technology. Dr. Ouyang is also a recipient of the “New Century Talent” award (Ministry of Education) in 2013, when he was working at Shandong University.
The research team analyzed the average diameter of the nanometer polar clusters (NPCs), the feature size for the short-range ordered SPE film, as a function of the film thickness. They found that the film’s NPC size, which is positively correlated with the film’s k value, is dictated by the temperature of the sputter-deposition, not the film thickness. “These observations suggest that the dominant factor for a scalable k in a SPE dielectric is its NPC size, not the film thickness usually being investigated. It is such a small feature size that has led to a good thickness scalability of k in a SPE ultrathin film, as opposed to a non-scalable k in its ferroelectric counterpart. Furthermore, through studies of the temperature dependence of k (k–T curves), we estimated the critical NPC size for the superparaelectric-to-paraelectric (SPE-PE) transition in the BSZT film, i.e., its theoretical scalability limit as a gate layer. This limit is between 1.3 and 1.8 nm, which is consistent with the thermodynamic prediction for the BSZT material,” Jun Ouyang said.
The research team outlines other unique properties of the superparaelectric BSZT films endowed by their aforementioned microstructure of “well-dispersed nanometer polar clusters (NPCs)”. These properties include a high breakdown strength (~10.5 MV·cm−1 for the 4 nm film), which ensures a low leakage current for the operation of the complementary metal oxide semiconductor (CMOS) gate. Moreover, a high electrical fatigue resistance, i.e., charge–discharge stability, was displayed by the SPE films. These results reveal a great potential of superparaelectric materials as gate dielectrics in the next-generation microelectronics.
The research team expects this work to spur development of new superparaelectric-based gate layers to further decrease the EOT value and help continue the Moore’s law.
Other contributors include Kun Wang, Chao Liu, Fuyu Lv, Hongbo Cheng, Hanfei Zhu from Qilu University of Technology, Yu-Yao Zhao and Yun Tian from Shandong University, Yuan Zhang from Southern University of Science and Technology, Houbing Huang and Xiaoming Shi from Beijing Institute of Technology, and Rui-long Yang from Shanxi Normal University.
This work was supported by the National Natural Science Foundation of China (Nos. 51772175 and 52002192), the Natural Science Foundation of Shandong Province (Nos. ZR2022ZD39, ZR2020QE042, ZR2022ME031, and ZR2022QB138), the Education Department of Hunan Province/Xiangtan University (No. KZ0807969), the Jinan City Science and Technology Bureau (No.2021GXRC055) and the Science, Education and Industry Integration Pilot Projects of Qilu University of Technology (Shandong Academy of Sciences) (Nos.2022GH018 and 2022PY055).
Journal
Journal of Advanced Ceramics
Article Title
Pushing the high-k scalability limit with a superparaelectric gate layer
Article Publication Date
30-Apr-2024