Solving combinatorial optimization problems with a scalable fully coupled annealing processor. (IMAGE)
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In a new study, researchers from TUS, Japan, proposed a fully connected scalable annealing processor that, when implemented in FPGA, can easily outperform a modern CPU in solving various combinatorial optimization problems in terms of speed and energy consumption. The proposed method achieves this using an “array calculator,” consisting of multiple coupled chips, and a “control chip.” It could be applied to solve similar complex optimization problems in logistics, network routing, warehouse management, personnel assignment, drug delivery, and materials science.
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Takayuki Kawahara from TUS, Japan
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