Figure 3a Scanning electron micrographs of a device, showing the various gates used to define the 1D wires (Part 1) (IMAGE)

University of Cambridge

Figure 3a Scanning electron micrographs of a device, showing the various gates used to define the 1D wires (Part 1)

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Figure 3a Scanning electron micrographs of a device, showing the various gates used to define the 1D wires (Part 1)

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Research Team, Cavendish Laboratory, Department of Physics, University of Cambridge

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