Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

Tokyo Institute of Technology

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL)

Caption

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB.

Credit

ISSCC 2024

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