ITHACA, N.Y. -- Push a number on a palm-sized cell phone and the signal travels to an interior chip with physical features some five orders of magnitude smaller than the number button. That connection is called "electronic packaging," and the challenges presented by this huge discrepancy in size are becoming a serious problem for microelectronics.
One of the largest industry-financed research efforts to find answers to this packaging dilemma is under way at Cornell University, headed by J. Peter Krusius, professor of electrical engineering. His goal is to bridge the growing gap between the world of human dimensions -- the finger or the eye -- and the world of the ultrasmall -- the microchip. Recently Krusius was awarded a $330,000 contract by the Semiconductor Research Corp. (SRC), an industrial research consortium, to continue his investigation into so-called electronic packaging interconnect sciences, which it has supported with awards to Cornell totaling $6.4 million over the past 15 years. The research is part of the Electronic Packaging Program at Cornell, which also is supported by funding from the National Science Foundation and the Industry-Cornell University Alliance for Electronic Packaging.
Cornell has one of six programs for packaging research supported by the SRC, the others being at Stanford University, the Massachusetts Institute of Technology, Rensselaer Polytechnic Institute, the State University of New York at Albany and the Georgia Institute of Technology.
Krusius explains that packaging has to bridge the gap from the largest size to the smallest size in the system, whether it be in a telephone or a radio. A cellular phone, for example, has a number button on the order of 10 millimeters in diameter, but the smallest feature on the chip inside the phone, such as interconnect lines and transistor parts, is on the order of less than half a micrometer in diameter. That is almost five orders of magnitude difference in size from outside to inside. If nanotechnology is able to reduce devices on chips to nanodots -- tiny circuit islands a few atoms across -- the size difference between the outside and the inside of a device would be seven to eight orders of magnitude.
"The problem is that these electronic packages are getting more and more complex, and we are asking more and more of them. Consequently the costs are going up faster than that of the chips themselves. People in the industry are greatly worried," says Krusius.
Indeed, reducing the size of devices is no longer only a chip issue, he says, but, more important, a packaging issue.
The answer -- and this is the area that is occupying three groups of packaging interconnect researchers at Cornell -- is to find a way of allowing information and energy and system support to travel from the outside of the device to the inside: in other words, to allow a very large thing to talk to a very small thing.
Traditionally, the hundreds of interconnections in packages -- the bridges from the package to the chip -- have been made on the periphery of the chip. Instead, Krusius and his team are looking at constructing an array of tiny connections, possibly tens of thousands, to the entire bottom area of the chip. The task, though, is to find connection materials, such as a solder, that would not shear off as it expands from the heat generated by the chip. That problem is being investigated by a group led by Che-Yu Li, Cornell's F.N. Bard Professor of Materials Science and Engineering.
A second problem is that such a dense array of connections would have to be protected in some way to prevent electrical interactions caused by their proximity. "The closer you bring the connections together, the more serious are the interactions," says Krusius, who is leading this task research group.
The third problem is developing capacitors, possibly from composite films containing nanocrystals, that could be placed as close as possible to the connections. Capacitors are filters that clean up electrical interference and also store electrical energy to prevent information loss. This research group is headed by Emmanuel Giannelis, Cornell professor of materials science and engineering.
Looking ahead over the next decade, Krusius sees "serious constraints" arising from the packaging problem that might prevent devices from "going all the way to the lowest level on the nanometer scale." Does this mean that the "Star Trek" two-way lapel button radio really is science fantasy? The answer to whether it's possible or not, says Krusius, lies in the packaging.
Related World Wide Web sites: The following sites provide additional information on this news release. Some might not be part of the Cornell University community, and Cornell has no control over their content or availability.
-- Cornell Electronic Packaging Program: http://www.afep.cornell.edu/
-- Semiconductor Research Corp.: http://www.src.org