CHAMPAIGN, Ill. - A new chemical process for the deposition of titanium
disilicide -- a crucial component of silicon-based semiconductors -- shows
promise as a method of fabricating smaller, faster microelectronic devices,
a University of Illinois researcher says.
The process, which has been patented, can deposit a thin layer of titanium
disilicide on submicron-scale device structures in a fashion compatible
with current manufacturing methods -- a goal that has eluded researchers
for years.
"Titanium disilicide is widely used for making contacts to transistors
in integrated circuits," said Edmund Seebauer, a professor of chemical
engineering. "The current technology used to make this material involves
reacting metallic titanium with the underlaying silicon substrate at high
temperature. Because of problems associated with substrate consumption,
dopant diffusion and film agglomeration, this technique cannot be scaled
to smaller, next-generation devices."
To avoid these problems, the microelectronics industry turned to an alternate
fabrication technique -- chemical vapor deposition (CVD). Despite a decade
of trial-and-error work on a replacement CVD process, no satisfactory results
were achieved.
Recently, Seebauer and graduate students Mike Mendicino and Robert Southwell
took a different approach. First, they devised a series of experiments under
carefully controlled conditions and at low pressures that permitted precise
measurements of the various reaction rates involved with the CVD process.
Then, based on the measured reaction rates, a mathematical model was created
to predict what should occur at the much higher pressures required for practical
applications. Finally, they compared the deposition of titanium disilicide
produced under actual operating conditions with what their model had predicted.
The results matched nearly perfectly.
"By injecting the reactants in a gas phase at lower temperature, the
CVD process avoids problems with substrate consumption, phase transformation
and high-temperature agglomeration," Seebauer said. "Therefore,
this chemical process can be used on much smaller device structures.
"We have developed a kinetic methodology for fully modeling the chemical
vapor deposition of titanium disilicide," Seebauer said. "This
work represents to our knowledge the first time such kinetic models have
successfully guided the a priori development of a practical process
governed by surface reactions in which optimization has not already been
accomplished by enlightened trial and error."
Currently, the new chip chemistry is being scaled up to accommodate the
large wafer sizes used in the commercial production of integrated circuits.
"In a general sense, this work also can serve as a template for the
difficult and heretofore largely unsuccessful business of a priori
optimization of other practical surface reactions," Seebauer said.