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Cornell Materials Scientists Smooth Out Atomic Wrinkles On The Surface Of Silicon Wafers

Cornell University



This scanning tunneling microscope image of a typical silicon wafer surface, taken at Cornell, shows steps each of a height corresponding to one atom spacing. Here, four atomic steps are separated by flat atomic planes, or terraces. Rows of silicon atoms are clearly visible on the terraces. Cornell materials scientists have developed a process to increase the areas of perfect atomic terraces by a factor of greater than 1,000, producing a step-free surface.

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ITHACA, N.Y. -- Cornell University materials scientists have come up with a novel technique that could vastly improve the performance and yield of silicon microelectronic and optical devices, which are used in semiconductor integrated circuits that power everything from computers to telephones.

One of the problems in further miniaturization of devices is that the surface of silicon wafers -- the platform on which computer chips are made -- can be irregular at the atomic level. Crystals of silicon are made up of sheets of atoms stacked in a very regular way. The surfaces of the crystalline wafers ideally would consist of a smooth atomic plane with all the atoms at the same level. On real surfaces, however, the level of the surface varies from one spot to another so that the real surface consists of short, smooth terraces each ending in a step of atomic dimensions -- a distance of about 1.5 nanometers. Cornell materials scientists have created arrays of atomically flat silicon surfaces -- essentially eliminating these atomic steps and overcoming one of the major hurdles to further miniaturization.

In current manufacturing technology, these atomic steps are not a problem because devices are not yet small enough for an exactly flat surface to be necessary. But the next generation of integrated circuits will require silicon surfaces that are perfectly smooth.

"We are able to create extensive regions on a silicon wafer that have no atomic steps," said Jack Blakely, Cornell professor of materials science and engineering who led the work. "Silicon wafers can be patterned to have larger areas that are totally step-free."



An atomic force microscope image of a silicon surface with structures fabricated by Cornell materials scientists, before the regions have been cleared of atomic steps. The scientists made this grid to serve as atomic boundaries. The ridges are about 1 micron wide and 0.5 micron high, or about 1,000 atoms high, making 10 micrometer-wide squares. The result: silicon wafers that are perfectly smooth, with no atomic steps.

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The benefit: "It should now be feasible to make smaller devices with better control of the dimensions, at the atomic level, and it should eliminate the harmful features of the surface that could get through the manufacturing process," Blakely said.

Blakely and co-authors So Tanaka, a doctoral student in his lab; C.C. Umbach, former Blakely doctoral student now a Cornell research associate; and Ruud M. Tromp and M. Mankos of IBM Watson Research Laboratory in Yorktown Heights, N.Y., describe their work in the journal Applied Physics Letters (Aug. 26, 1996) in a paper, "Fabrication of Arrays of Large Step-Free Regions on Silicon Wafers." Cornell Research Foundation has applied for a patent on the technology and is seeking a licensing partner. The work was funded by a grant to Blakely's research group at Cornell by the National Science Foundation and by the NSF-funded Materials Science Center at Cornell.

Here is how they did it: The scientists created a grid of ridges on the surface of the wafer and cleared the intervening squares of their atomic steps by forcing them into the ridges. Think of it as the way a farmer might clear a square field by moving all the boulders out to the edges. The boulders become localized in the wall surrounding the field.

In this case, the researchers created the grid at the Cornell Nanofabrication Facility using electron beam lithography, which made a series of ridges that serve as boundaries. Each square, about 10 micrometers wide, has about a billion atoms on it, with several thousand atomic steps all across the square. The ridges are about 0.5 micrometers high and 1 micrometer wide.



Images from a low energy electron microscope (LEEM) shows, a.) an unpatterned region of a silicon wafer. The dark regions and lines are atomic steps, which makes the surface of the silicon wafer irregular. Through a processing technique developed by Cornell materials scientists, b.), those steps are moved along to the edges, until quite extensive step-free regions can be seen (c.). Finally, d.) the entire flat region of the wafer is step-free. Such processing could vastly improve the next generation of semiconductor devices.

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They subjected the sample to ultra-high vacuum and then high temperatures, within the window 1,020 to 1,150 degrees Centigrade. At these temperatures, silicon atoms are detached from the atomic steps so that the steps migrate to the ridges at the boundary of the square, leaving the surface of the square atomically flat.

The Cornell team has made grids with dimensions from 2 micron-wide to about 50 micron- wide squares, and were successful in clearing the atomic steps up to about 10 microns. The step-free regions are arranged in a regular array so that an entire wafer could be prepared for manufacture of devices all on step-free surfaces.

They confirmed what they had achieved by using low energy electron microscopy at the IBM Watson Research Lab in Yorktown Heights, N.Y., to get pictures of the atomic steps. Previous work in this area used a scanning tunneling microscope at Cornell, that Blakely and his group built, using resources of Cornell's Materials Science Center.

An advantage to this technique is that all the technology is currently available and industry already has the tools.

"It is easily implemented, too," Blakely said. "Circuits built on step-free surfaces can be designed with smaller dimensions and utilize thinner semiconductor channels and insulating layers to increase performance and decrease power consumption. By having it flat, this could be an ideal surface on which to build an integrated circuit."

He added, "It's a very simple technique, so it has some elegance due to its simplicity."

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