Figure 2. Die micrograph of the proposed transceiver (image) Tokyo Institute of Technology Share Print E-Mail Caption The proposed phased-array transceiver is fabricated using a 65-nm CMOS process and packaged with wafer-level chip-scale package. It is configured in an area as small as 5 × 4.5 mm. Credit 2021 Symposia on VLSI Technology and Circuits Usage Restrictions None Share Print E-Mail Disclaimer: AAAS and EurekAlert! are not responsible for the accuracy of news releases posted to EurekAlert! by contributing institutions or for the use of any information through the EurekAlert system.