Fig. 2. (IMAGE)

Institute of Electrical and Electronics Engineers

Fig. 2.

Caption

Concept of μTP. (a) Pre-fabrication of III-V devices on their native substrate in dense arrays and the μTP integration on a target Si substrate. (b) Illustration of the integration of III-V-on-Si devices on a Si photonic wafer with back-end layers. Only a local opening (recess) is required to enable close contact of the III-V components to the Si device layer. Reproduced with permission from J. Zhang et al., in APL Photonics (invited), 4, p.paper 110803, doi:10.1063/1.5120004 (2019). AIP publishing.

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