New Digital PLL (IMAGE) Tokyo Institute of Technology Caption This is the proposed fractional-N DPLL occupies an area of 0.25 mm2 in 65-nanometer CMOS. Credit Kenichi Okada Usage Restrictions None License Licensed content Disclaimer: AAAS and EurekAlert! are not responsible for the accuracy of news releases posted to EurekAlert! by contributing institutions or for the use of any information through the EurekAlert system.