figure 1 (IMAGE)
Caption
(a) A schematic structure of a ferroelectric memory device developed by introducing hafnia-based ferroelectrics and an oxide semiconductor. While securing a low operating voltage and fast operating speed through a new material and structure, an oxide semiconductor was introduced as a channel material to lower the process temperature and suppress the formation of an interfacial layer to achieve high operating stability. (b) An image of ferroelectric NAND flash memory array. A ferroelectric NAND flash memory array was realized based on the newly developed ferroelectric memory. (c) A schematic structure and (d) an image of the 3D vertical ferroelectric memory device. Using the atomic layer deposition, a 3D vertical structure of a ferroelectric memory device was fabricated. (e) A schematic structure of the 3D vertical ferroelectric NAND flash memory. It was confirmed that the newly developed ferroelectric memory can be applied to ultrahigh-density 3D memory through device simulations.
Credit
POSTECH
Usage Restrictions
None
License
Licensed content