Schematic of New 4-Layer, High-Rise Chip (IMAGE)

Stanford University School of Engineering

Schematic of New 4-Layer, High-Rise Chip

Caption

This illustration represents the four-layer prototype high-rise chip built by Stanford engineers. The bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic "elevators" that connect logic and memory, allowing them to work together to solve problems.

Credit

Max Shulaker, Stanford

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