The test chip and system board (IMAGE)
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The top left shows a photo of the system test board, with a red box indicating Darwin3. The top right displays the top-level view of the chip layout, while below are the layout details of the main modules. The chip’s structure is organized into a grid of 6*6 groups, each consisting of 4*4 tiles. Each tile comprises a node connected to a router. Except for the RISC-V node, all nodes on the chip are neuron cores, collectively driving their computational functions. Notably, two distinct tile types exist, primarily differing in the size of their axon-in memory.
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